Earlier this week I posted a small write-up comparing a hardware median calculation implemented in a C-to gates "HLS" (Vivado C HLS) and a version in MyHDL.  For a long time I have had the belief that C-to-gate technologies are of little to no benefit - based on the simple premise that "C" is not that high-level of a language (I actually consider it lower than Verilog and VHDL ... but that is a conversation for another time).

Language comparisons...

## Little to no benefit from C based HLS

April 4, 2014

Last updated 07-Nov-2015

As I write this I am on a plane and my destination is EELive 2014 where I am going to give a talk hardware design: the grunge era.  It is a shotgun introduction to three alternative hardware description languages (alt.hdl). The three languages briefly introduced in the talk are: bsv, chisel, and myhdl.  The goal of the talk is simply to raise awareness of the three...

## Signed serial-/parallel multiplication

February 16, 2014

Keywords: Binary signed multiplication implementation, RTL, Verilog, algorithm

Summary
• A detailed discussion of bit-level trickstery in signed-signed multiplication
• Algorithm based on Wikipedia example
• Includes a Verilog implementation with parametrized bit width
Signed serial-/parallel multiplication

A straightforward method to multiply two binary numbers is to repeatedly shift the first argument a, and add to a register if the corresponding bit in the other argument b is set. The...

## MyHDL Interface Example

MyHDL Interfaces Example

With the next release of MyHDL, version 0.9, conversion of interfaces will be supported.  In this context an interface is any object with a Signal attribute.  This can be used to simplify connection between modules and port definitions.  For example, if I want to define a simple memory-map bus, the Signals for the bus can be defined as follows:

class BareBoneBus: def __init__(self): self.wr = Signal(False) self.rd =...

## MyHDL @EDAPlayground

October 24, 2013

Trying out MyHDL became a little easier recently.  MyHDL is now avaialbe @EDAPlayground.  One can experiment with Python/MyHDL verification of HDL modules and implementing complex digital cirucits in MyHDL.

The @EDAPlayground has two main panels. On the left is the testbench and the right the HDL description to be tested.

There are a couple examples...

## BGA and QFP at Home 1 - A Practical Guide.

It is almost universally accepted by the hobbyists that you can't work with high-density packages at home.  That is entirely incorrect.  I've been assembling and reflowing BGA circuit boards at home for a few years now.  BGAs and 0.5mm-pitch QFPs are well within the realm of a determined amateur.

This series of articles presents practical information on designing and assembling boards with high-density packages at home.  While the focus is on FPGA packages, most of...

## Windows XP and Win32 - the Platform of the Future!

Over the past decade I often wondered why anyone uses Windows.  It's just so... proprietary.  And pedestrian.  As I grew up my OS of choice went nothing to CPM to DOS (on Apple ][), GEM on Atari ST,  MS-DOS, DOS extenders, Mac OS, Windows NT, Windows XP, Linux...  Now, I again find myself a fan of Windows XP, the platform of the future.  (I am still a fan of bare metal, of course).Maybe I am not totally serious, but I, a self-proclaimed freedom lover and...

## Introducing the VPCIe framework

Introduction

My daily work involves platforms featuring an embedded CPU communcating with a FPGA device over a PCI Express link (PCIe for short). The main purpose of this link is for the CPU to convey configuration, control, and status commands to hardware slaves implemented in the FPGA. For data intensive applications (2D XRay detector readout backend), this link can also be used as a DMA channel to transfer data from the FPGA to the CPU memory. Finally, a slave can interrupt the CPU using...

## binary hello world

Python + Ohio + MyHDL + FPGA

Recently I had the opportunity to coordinate a hands-on programmable hardware (FPGA) workshop (open-space) at a regional Python conference - @pyohio. The workshop was for those that had little to no exposure to programmable hardware. For this situation I used two basic examples: two versions of a binary hello world.

The binary hello world -- blinking an LED -- is a good starting point to introduce programmable hardware, hardware descriptions languages,...

## Tool install for examples

Most of my examples on fpgarelated use MyHDL for the hardware description and another Python package myhdl_tools rhea.build to control the FPGA vendor's software. This means everything is controlled and run from the Python environment.

Install the following to compile the posted examples:

MyHDL package : pip myhdl or myhdl github myhdl_tools : myhdl_tools bitbucket rhea...

I thought it would take me a day or two to implement, it took almost two weeks...

But here it is, the new comments systems for blogs, heavily inspired by the forum system I developed earlier this year.

Which means that:

• You can easily add images, either by drag and drop or through the 'Insert Image' button
• You can add MathML, TeX and ASCIImath equations and they will be rendered with Mathjax
• You can add code snippets and they will be highlighted with highlights.js
• You can edit...

## Introducing the VPCIe framework

Introduction

My daily work involves platforms featuring an embedded CPU communcating with a FPGA device over a PCI Express link (PCIe for short). The main purpose of this link is for the CPU to convey configuration, control, and status commands to hardware slaves implemented in the FPGA. For data intensive applications (2D XRay detector readout backend), this link can also be used as a DMA channel to transfer data from the FPGA to the CPU memory. Finally, a slave can interrupt the CPU using...

## FPGA Bloggers Needed - New Reward System

Are you an FPGA expert? If you are an have an interest in sharing your knowledge with the FPGA community, you might be interested in the new reward system for bloggers (see the blogs section here).

The rewards will be based on page impressions, meaning that the more traffic a blog post will get, the faster it will generate rewards for the author.

Basically, a given blog post will generate $25 to the author for every 250 unique pageviews, up to a maximum total reward of$500 per blog post...

## An absolute position encoder VHDL core

November 11, 2015
Introduction

Let's consider motorized systems controlled by electronics. A closed loop architecture looks like this:

The following components are involved:

• the motor itself (DC, stepper ...),
• the controller, in charge of computing position according to the whole system state,
• the driver board in charge of generating signals and power for the motor,
• the position encoder, the subject of this post.

Most of the time, there is a difference between the position the system...

## Who else is going to Sensors Expo in San Jose? Looking for roommate(s)!

This will be my first time attending this show and I must say that I am excited. I am bringing with me my cameras and other video equipment with the intention to capture as much footage as possible and produce a (hopefully) fun to watch 'highlights' video. I will also try to film as many demos as possible and share them with you.

I enjoy going to shows like this one as it gives me the opportunity to get out of my home-office (from where I manage and run the *Related sites) and actually...

## Free Goodies from Embedded World - What to Do Next?

I told you I would go on a hunt for free stuff at Embedded World in order to build a bundle for someone to win.

## Free Goodies from Embedded World - Full Inventory and Upcoming Draw Live-Streaming Date

March 22, 2019

Chances are that you already know that I went to Embedded World a few weeks ago and came back with a bag full of "goodies".  Initially, my vision was to do a single draw for one person to win it all, but I didn't expect to come back with so much stuff and so many development kits.   Based on your feedback, it seems like you guys agree that It wouldn't make sense for one person to win everything as no-one could make good use of all the boards and there would be lots of...

## Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally

November 22, 2018

This article will look at a design approach for feedback controllers featuring  low-latency "irrational" characteristics to enable the creation of physical components such as transmission lines. Some thought will also be given as to the capabilities of the currently utilized Intel Cyclone V, the new Cyclone 10 GX and the upcoming Xilinx Versal floating-point FPGAs/ACAPs.

Fig 1. Making a Transmission Line, with the Circuit Emulator

## Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop

July 9, 2018

It's time to put together the DSP and feedback control sciences, the evaluation electronics, the Intel Cyclone floating-point FPGA algorithms and the built-in control loop test-bed and evaluate some example designs. We will be counting the nanoseconds and looking for textbook performance in the creation of emulated hardware circuits. Along the way, there is a printed circuit board (PCB) issue to solve using DSP.

Fig 1. The evaluation platform

## USB-FPGA : Introduction

January 12, 20111 comment

This blog is an introduction to a series of blogs I hope to write.  The blogs will cover the design and experiences I had on a project that spanned the last 6 years.  The project was the development of an USB FPGA board and the supporting gateware, firmware, and software.  The project has had different levels of activity over the years, ranging from none to some, but it has been an ongoing project, albeit, during sleepless nights.  Lately, I have ported the HDL (gateware)...