FPGARelated.com

Welcoming MANY New Bloggers!

Stephane Boucher October 27, 20153 comments

The response to the latest call for bloggers has been amazing and I am very grateful.

In this post I present to you the individuals who, so far (I am still receiving applications at an impressive rate and will update this page as more bloggers are added),  have been given access to the blogging interface.  I am very pleased with the positive response and I think the near future will see the publication of many great articles, given the quality of the...


Recruiting New Bloggers!

Stephane Boucher October 16, 20157 comments

Previous calls for bloggers have been very successful in recruiting some great communicators - Rick LyonsJason Sachs, Victor Yurkovsky, Mike Silva, Markus NentwigGene BrenimanStephen Friederichs,


Summer of Gateware

Christopher Felton September 18, 2015

This (last) summer the MyHDL project participated in the Google Summer of Code (GSoC) as a sub-organization under the Python Software Foundation (PSF). This was our first year participating - there was a lot for us to learn.  Overall it was a worthwhile and beneficial activity.

Being a first time sub-org we were limited to a maximum of two students.  We had nine students apply and twelve mentors volunteer.  Only being able to select two students...


Tools of the Trade: reading PDFs (and keeping bookmarks)

Victor Yurkovsky July 7, 20155 comments

In this article I will take a look at the wonderful MuPDF viewer and present a small modification that saves bookmarks alongside the pdf files, making it infinitely more useful.

Some days I sit down to work and wonder how anything ever gets done. A simple example.  When I work on an FPGA design, I wind up with 3 or 4 screens full of documentation, generally in PDF format.  There are the Xilinx manuals, the various tool manuals, language reference manuals, you name it.  While...


Inside the Spartan-6: Using LUTs to optimize circuits

Victor Yurkovsky June 24, 20153 comments

While building a small CPU on a Spartan-6 chip I came across the same old problem: my Verilog was mapping to a lot of slices . Way more then seems reasonable. So let's dig in and see what's really going on.  

The J1 CPU (see Messing Around with a J1) is an amazingly streamlined design expressed in just over 100 lines of Verilog, and is reasonably compact at 150 Spartan-6 slices (half of that with the modifications described in the article).  But the Picoblaze is...


Homebrew CPUs: Color Languages

Victor Yurkovsky June 17, 2015
Color Languages

Here on bizarro we program using -- get this – text!  Our other senses - hearing, touch, smell, are not used at all. Even our visual perception is greatly underutilized - we just use two-dimensional text on a flat display a foot in front of our eyes.

Color is just beginning to be used, although in a lame syntax coloring way only. Granted, it makes it easier to detect stupid syntax errors such as misspelled keywords. Sadly, color carries zero semantic or...


Homebrew CPUs: Messing around with a J1

Victor Yurkovsky May 29, 2015

In this article I will examine James Bowman's excellent J1 CPU; I will then proceed to mess around with various parts of it, making it smaller, more appropriate to my particular application, and possibly faster.  I hope this will show you how easy it is to fiddle around with homemade CPUs and encourage you to make something weird and wonderful.

J1 CPU

My hat is off to James Bowman.  J1 is pretty cool.  It is a stack machine; it executes instructions in one cycle, it is...


Makefiles for Xilinx Tools

Victor Yurkovsky May 12, 20155 comments

Building a bitstream from an HDL is a complicated process that requires the cooperation of a lot of tools.  You can hide behind an IDE or grow a pair and use command line tools and a makefile to tie your build process together.  I am not a huge fan of makefiles either (I believe a language should be expressive enough to automate the build process), but the alternatives are dismal. 

Command-line driven workflow is easier on the hands and faster.  The example...


Use a Simple Microprogram Controller (MPC) to Speed Development of Complex Microprogrammed State Machines

Michael Morris April 18, 20152 comments
Introduction

This article will describe a synthesizable HDL-based microprogram controller (MPC), or microprogram sequencer (MPS), that can be used to provide the control of a microprogrammed state machine. Unlike the microprogrammed state machines that I described in my previous two articles, "Use Microprogramming to Save Resources and Add Functionality" and "Fit Sixteen (or more) Asynchronous Serial Receivers in the Area of a Standard UART", many microprogrammed state machines will...


Fit Sixteen (or more) Asynchronous Serial Receivers into the Area of a Standard UART Receiver

Michael Morris March 29, 20155 comments
Introduction

This article will describe a technique, available in many current FPGA architectures, to fit a large amount of logic into a small area. About ten years ago now (Feb/Mar 2005), I helped develop a multi-line Caller ID product. The Multi-Channel Asynchronous Receiver (MCAR) FPGA core developed for that product will be used to illustrate the technique(s) needed to fit a 16 channel MCAR into a single Spartan II XC2S30-5VQ100 FPGA.

To stay true to the original design, I...


Designing Embedded System with FPGA - 1

Pragnesh Patel October 28, 200711 comments

With the introduction of soft processors and related tools (like EDK from Xilinx), implementation of basic embedded system in FPGA is made easy. This requires very little or almost no knowledge of VHDL programming. Actually that’s how I started. If user is interested in taking full advantage of FPGA and its parallel processing power, then yes, detail understanding of soft processor, its peripheral bus and VHDL programming is required.

 

I will start with...


How precise is my measurement?

Sam Shearman March 28, 20183 comments

Some might argue that measurement is a blend of skepticism and faith. While time constraints might make you lean toward faith, some healthy engineering skepticism should bring you back to statistics. This article reviews some practical statistics that can help you satisfy one common question posed by skeptical engineers: “How precise is my measurement?” As we’ll see, by understanding how to answer it, you gain a degree of control over your measurement time.

An accurate, precise...

Welcoming MANY New Bloggers!

Stephane Boucher October 27, 20153 comments

The response to the latest call for bloggers has been amazing and I am very grateful.

In this post I present to you the individuals who, so far (I am still receiving applications at an impressive rate and will update this page as more bloggers are added),  have been given access to the blogging interface.  I am very pleased with the positive response and I think the near future will see the publication of many great articles, given the quality of the...


SEGGER's 25th Anniversary Video

Stephane Boucher July 18, 20172 comments

Chances are you will find this video more interesting to watch if you take five minutes to first read the story of the week I spent at SEGGER's headquarters at the end of June.  

The video is only a little more than 2 minutes long.  If you decide to watch it, make sure to go full screen and I would really love to read your thoughts about it in the comments down bellow.  Do you think a video like this succeeds in making the viewer want to learn more about the company?...


Feedback Controllers - Making Hardware with Firmware. Part I. Introduction

Steve Maslen August 22, 2017
Introduction to the topic 

This is the 1st in a series of articles looking at how we can use DSP and Feedback Control Sciences along with some mixed-signal electronics and number-crunching capability (e.g. FPGA), to create arbitrary (within reason) Electrical/Electronic Circuits with real-world connectivity. Of equal importance will be the evaluation of the functionality and performance of a practical design made from modestly-priced state of the art devices.

  • Part 1: 

An absolute position encoder VHDL core

Fabien Le Mentec November 11, 2015

In this article, Fabien Le Mentec explains how to implement a unique VHDL core addressing absolute position encoder interfaces. He reviews existing instruments in use or being developed and considers their specific requirements. He also looks for details in current implementations and considers the projects to come so that the implementation can be designed to be extensible. The VHDL core dubbed absenc features both ENDAT, BISS and SSI interface. Due to its architecture, new interfaces are easily added. Also, the 3 interfaces can be enabled at synthesis while 1 is selected at runtime. As much as possible, resources common to the different interfaces are shared (counters, comparators…).


FPGA Assemblers and Time Machines

Victor Yurkovsky September 2, 20121 comment

Flashback to 1986. A young man has a crazy idea - he wants to make a CPU all by himself. He is reading early Xilinx manuals cover to cover as if they were novels. Yes, you are quick - this is indeed a (mostly) true story about me and my dream, suddenly made possible by this new FPGA technology.

Sadly more than 20 years went by before my first CPU ran in a Xilinx FPGA. Why did it take so long? Every few years I set up the tools and every time I walked away, scared silly. As the years...


Going back to Germany!

Stephane Boucher June 13, 20176 comments

A couple of blog posts ago, I wrote that the decision to go to ESC Boston ended up being a great one for many different reasons.  I came back from the conference energized and really happy that I went.  

These feelings were amplified a few days after my return when I received an email from Rolf Segger, the founder of SEGGER Microcontroller (check out their very new website), asking if I would be interested in visiting their headquarters...


Who else is going to Sensors Expo in San Jose? Looking for roommate(s)!

Stephane Boucher May 29, 20186 comments

This will be my first time attending this show and I must say that I am excited. I am bringing with me my cameras and other video equipment with the intention to capture as much footage as possible and produce a (hopefully) fun to watch 'highlights' video. I will also try to film as many demos as possible and share them with you.

I enjoy going to shows like this one as it gives me the opportunity to get out of my home-office (from where I manage and run the *Related sites) and actually...


3 Good News

Stephane Boucher March 9, 20161 comment
Good News #1

Last week, I announced a new and ambitious reward program that will be funded by the new Vendors Directory.

This week, I am happy to announce that we have our firsts two sponsors!  Quantum Leaps & Abelon Systems have agreed to pay the sponsorship fee to be listed in the new Vendors Directory.  Because of their support, there is now some money in the reward pool ($1,000) and enough to pay for the firsts 500 'beers' awarded.  Please...