Dealing With Fixed Point Fractions
Fixed-point fractional math is easy to botch, and this post lays out pragmatic ways to avoid those mistakes. It clarifies the difference between integer and fractional overflow, shows how Q notation helps track binary-point scaling, and explains why multiplies add sign bits that may require shifting. Read for concrete FPGA strategies: keeping bit growth, selective shifts, or aggressive normalization, plus testing tips.
Mathematics and Cryptography
Cryptographic math can look intimidating, but this roundup trims it to what FPGA engineers actually need. It groups concise articles on number theory and elliptic curves, focusing on polynomial math over Galois fields, FPGA-friendly inversion and one-clock-cycle techniques, and elliptic-curve key exchange and digital signatures. Read this to learn which subroutines to implement first and how to turn math into Verilog or VHDL.
Elliptic Curve Digital Signatures
Elliptic curve digital signatures deliver compact, strong message authentication by combining a hash of the message with elliptic curve point math. This post walks through the standard sign and verify equations, showing why recomputing a point R' yields the same x coordinate only when the hash matches. It also explains the Nyberg-Rueppel alternative that removes modular inversion and an FPGA-friendly trick of transmitting point D to avoid integer modular arithmetic.
Elliptic Curve Key Exchange
Elliptic Curve key exchange gives a fresh secret for every session so past messages stay safe even if one key is discovered. This post walks through an ElGamal-style ephemeral exchange and the MQV protocol, showing how MQV mixes static and random keys to provide mutual authentication and forward secrecy. It also explains how MQV can be implemented using only curve operations to save FPGA area and why erasing ephemeral values matters.
Discrete-Time PLLs, Part 1: Basics
In this series of tutorials on discrete-time PLLs we will be focusing on Phase-Locked Loops that can be implemented in discrete-time signal proessors such as FPGAs, DSPs and of course, MATLAB.
Polynomial Inverse
One of the important steps of computing point addition over elliptic curves is a division of two polynomials.
One Clock Cycle Polynomial Math
Error correction codes and cryptographic computations are most easily performed working with GF(2^n)
Elliptic Curve Cryptography
Secure online communications require encryption. One standard is AES (Advanced Encryption Standard) from NIST. But for this to work, both sides need the same key for encryption and decryption. This is called Private Key encryption.
An absolute position encoder VHDL core
In this article, Fabien Le Mentec explains how to implement a unique VHDL core addressing absolute position encoder interfaces. He reviews existing instruments in use or being developed and considers their specific requirements. He also looks for details in current implementations and considers the projects to come so that the implementation can be designed to be extensible. The VHDL core dubbed absenc features both ENDAT, BISS and SSI interface. Due to its architecture, new interfaces are easily added. Also, the 3 interfaces can be enabled at synthesis while 1 is selected at runtime. As much as possible, resources common to the different interfaces are shared (counters, comparators…).
Helping New Bloggers to Break the Ice: A New Ipad Pro for the Author with the Best Article!
Breaking the ice can be tough. Over the years, many individuals have asked to be given access to the blogging interface only to never post an article.
Going back to Germany!
A conference conversation turned into a return trip to Germany for Stephane Boucher, this time to visit SEGGER’s headquarters in Dusseldorf and produce videos. The post shares how a chance introduction at ESC Boston led to the invitation, and it teases coverage from SEGGER’s 25th anniversary celebration. He also invites local tips and customer questions before the trip.
PC and SP for a small CPU
Victor Yurkovsky walks through a compact stack-based CPU idea that tosses the conventional PC register in favor of a return stack living in Xilinx distributed RAM. The clever twist uses the stack memory addressed by SP as the program counter, making calls trivial and keeping the design tiny. The article shows the Verilog stack module and explains the practical tradeoffs of isolating the return stack.
MyHDL synthesis: from browser to FPGA in five seconds
Martin Strubel walks through how modern open-source tooling slashes the pain of converting super-HDLs into FPGA-ready firmware. Instead of long translation chains from MyHDL or nMigen into Verilog or VHDL, yosys and its Python API let you build synthesizeable primitives on the fly, inspect schematics, and emit synthesized Verilog or firmware quickly. The post explains the shift from toolchain friction to fast browser-to-FPGA workflows.
Feedback Controllers - Making Hardware with Firmware. Part I. Introduction
This first post kicks off a series on using DSP and feedback control with mixed-signal electronics and FPGAs to emulate two-terminal circuits and create low latency controllers. It frames circuit emulation as a feedback problem, highlights latency as the key practical constraint, and outlines the planned evaluation hardware, target devices, and software tools that will be used in later MATLAB/Simulink and FPGA work.
Recruiting New Bloggers!
EmbeddedRelated is expanding its blogging team, and Stephane Boucher is inviting engineers, students, hobbyists, and researchers to contribute. He points to the success of earlier contributors and says the community has already read their articles more than 1,250,000 times. If you have knowledge to share, this post explains how to pitch a topic and get started.
Windows XP and Win32 - the Platform of the Future!
Victor Yurkovsky makes the contrarian case that an offline Windows XP VM running Win32 is the most practical platform for modern FPGA development. He explains how Xilinx ISE and related tools often behave far better under XP than on modern Linux distributions, and how VirtualBox fixes USB and GUI headaches. If you maintain FPGA toolchains or write compact C/C++ utilities, this retro setup can save time and frustration.
Feedback Controllers - Making Hardware with Firmware. Part 5. Some FPGA Aspects.
This installment digs into practical FPGA choices and board-level issues for a low-latency, floating-point feedback controller. It compares a Cyclone V implementation against an older SHARC-based design, quantifies the tradeoff between raw DSP resources and cycle latency, and calls out Gotchas found on the BeMicro CV A9 evaluation card. Engineers get concrete prompts for where to optimize: clocking, DSP-block use, I/O standards, and algorithm partitioning.
New Comments System (please help me test it)
DSPRelated just got a practical upgrade, Stephane Boucher has released a new comments system built from his earlier forum work. It supports drag-and-drop or Insert Image uploads, MathML, TeX and ASCIImath rendered by MathJax, syntax-highlighted code via highlight.js, and in-place editing and deletion of comments. Improved email notifications alert authors and commenters to replies, and readers are invited to post test comments and report problems.
How to start in FPGA development? - Simulation software tools
Nuria Orduna lays out a pragmatic approach to FPGA simulation, comparing Xilinx ISE with integrated ModelSim against a three-tool flow with ModelSim and Precision. She explains why independent ModelSim runs and using notepad++ for VHDL can speed debugging, and why Precision and CoreGen conversions can be painful. Read for a compact, practiced workflow to simplify simulation, synthesis, and project organization.
New book on Elliptic Curve Cryptography
New book on Elliptic Curve Cryptography now online. Deep discount for early purchase. Will really appreciate comments on how to improve the book because physical printing won't happen for a few more months. Check it out here: http://mng.bz/D9NA
Finally got a drone!
Stephane Boucher finally bought a DJI Phantom 4 and found it does more than boost his video production value, it’s also hugely fun to fly. He used the drone for an aerial shot at SEGGER’s anniversary and for a beach project where kids drew a turtle while a separate camera captured a side timelapse. The post highlights creative shot combinations and a reminder to fly where it is legal.
Back from ESC Boston
Stephane nearly skipped ESC Boston, but going turned into a productive mix of networking, informal meetups, and on-the-floor filming. He captures candid encounters with speakers and vendors, learns how small shows differ from larger expos, and outlines practical follow-ups like booth highlight videos and speaker hospitality suggestions. The post is an encouraging read for engineers weighing the value of regional conferences and DIY event coverage.
Makefiles for Xilinx Tools
Building a bitstream from HDL is messy, and Victor Yurkovsky lays out a minimal, practical makefile workflow for Xilinx ISE and XST. He shows a simple project layout, techniques to tame ISE's generated logs and temps, and a ready-to-clone repo; an LED blinker example builds to bitstream in under 20 seconds on his machine. Use it as a pragmatic starting point for command-line FPGA builds.
Embedded World 2018 - More Videos!
Two cinematic videos from Embedded World 2018 turn the show floor into slow-motion, stabilized footage using a Zhiyun Crane gimbal and a Sony a6300. One is a SEGGER booth highlights piece featuring Rolf Segger and Axel Wolf, the other is a roaming montage with appearances from Jacob Beningo, Micheal Barr, and Alan Hawse. Stephane asks viewers to enable audio and share feedback.
Learning VHDL - Basics
Enrico Garante walks through a compact, hands-on introduction to VHDL and Xilinx ISE, using the affordable Basys2 board. The tutorial explains entity versus architecture, the IEEE.STD_LOGIC_1164 types, and how to write a process with a sensitivity list to implement a simple AND gate. A short ISim video demo shows project creation and simulation so you can verify designs before programming the board.
Embedded World 2018 - The Interviews
Stephane Boucher brought video gear to Embedded World 2018 and teamed up with Jacob Beningo to capture concise vendor interviews that focus on real product news. The videos showcase Percepio's new Tracealyzer with a drone demo, Intrinsic ID's method for creating device-unique IDs from manufacturing variations, and SEGGER's broader toolset including embOS now certified by TÜV SÜD. Watch for short demos and expert explanations.
Use Microprogramming to Save Resources and Increase Functionality
Microprogramming can rescue an overfull FPGA, Michael Morris shows, by compressing control logic and time-multiplexing FIFO storage. He replaces an ABEL state machine with a small microprogram ROM that uses block RAM for deep Rx/Tx FIFOs and LUT RAM for pointers and counters, freeing about 25 percent of the device. The article includes Verilog comparisons, resource tables, and a microassembler link to reproduce the approach.
SEGGER's 25th Anniversary Video
Stephane Boucher spent a week at SEGGER's headquarters and distilled that visit into a tight, two-minute 25th anniversary video. The post highlights rising production value, thanks to softbox lighting and a two-camera setup that allows seamless wide-to-tight cuts and emotional close-ups. Stephane invites readers to watch full screen, leave feedback and thumbs-up on YouTube, and suggests future coverage like product launches or companies with happy engineers.
Going back to Germany!
A conference conversation turned into a return trip to Germany for Stephane Boucher, this time to visit SEGGER’s headquarters in Dusseldorf and produce videos. The post shares how a chance introduction at ESC Boston led to the invitation, and it teases coverage from SEGGER’s 25th anniversary celebration. He also invites local tips and customer questions before the trip.
Crowdfunding Articles?
Technical writers in the embedded world often have the expertise, but not always the time or incentive to turn it into a post. Stephane Boucher explores a crowdfunding model for technical articles, where readers would pledge small amounts to back promising abstracts before the writing begins. It is an interesting attempt to create more high quality EE content by paying authors upfront.
