My VHDL <= monpjc; Journey
I always like to start my first blog on a website with a bit of a introduction as to who I am and what I’ll be writting about. I feel this gives you the reader a opportunity to see where I’m coming from and understand a little of my point of view. So when I was asked to come and start blogging on FPGARelated I wondered what I should say. So for my first blog its all about how me, aka monpjc, and how I got into VHDL.
It started a long time ago when I was working for a...
MyHDL FPGA Tutorial I (LED Strobe)
Last updated 05-Nov-2015
IntroductionFrom many perspectives the latest FPGA offerings from 'X' and 'A' are large devices - mucho programmable logic resources. Even the devices that one can get for sub \$10 are relatively large. Because of the size of these FPGAs they are implemented using an HDL. To manually configure each circuit would be a long and tedious task. It is not feasible to program an FPGA by manually defining the logic for each LUT and manually...
Oscilloscope Dreams
My coworkers and I recently needed a new oscilloscope. I thought I would share some of the features I look for when purchasing one.
When I was in college in the early 1990's, our oscilloscopes looked like this:
Now the cathode ray tubes have almost all been replaced by digital storage scopes with color LCD screens, and they look like these:
Oscilloscopes are basically just fancy expensive boxes for graphing voltage vs. time. They span a wide range of features and prices:...
FPGA or DSP Processor - Parameters to Make the Right Choice
Introduction
Digital Signal Processing (DSP) has a huge global market that is growing fast day by day with rapidly evolving sophisticated modern electronics applications like 3G wireless, voice over internet protocol (VoIP), multimedia systems, radar and satellite systems, medical systems, image-processing applications and consumer electronics. These sophisticated DSP applications pose many conflicting challenges to system designers and application developers in terms of cost and...
Using GHDL for interactive simulation under Linux
The opensource and free VHDL simulator 'GHDL' has been out for many years, but like many other opensource tools, it has caught limited attention from the industry. I can hear you thinking: 'If it doesn't cost money, it can't be worth it'. Well, I hope this short overview will change your mind and even whet your appetite for more. Because, using some extensions, you can do some quite funky stuff with it that will save you a lot of debugging work. For example, simulate your real world software...
VHDL tutorial - A practical example - part 3 - VHDL testbench
In part 1 of this series we focused on the hardware design, including some of the VHDL definitions of the I/O characteristics of the CPLD part. In part 2, we described the VHDL logic of the CPLD for this design. In part 3, we will show the entire VHDL design and the associated tests used to prove that we have, in fact, designed what we started out to design.
First, let's pull all of the pieces of the prior design together into a...
Verilog vs VHDL
Introduction
Verilog and VHDL are two industry standard Hardware Description Languages (HDL) that are used in writing programs for electronic integrated circuits (ICs) i.e., ASIC and FPGA. Many system designers face this issue: which HDL language to choose – Verilog or VHDL. The answer is by no means easy or trivial. Both of these languages are widely compared and contrasted without any clearly defined victor. Both of them have their own merits and demerits and have different...
VHDL tutorial - A practical example - part 2 - VHDL coding
In part 1 of this series we focused on the hardware design, including some of the VHDL definitions of the I/O characteristics of the CPLD part. In part 2, we will describe the VHDL logic of the CPLD for this design.
With any design, the first step to gather the requirements for the job at hand. From part 1 of this article, I have copied two sections that address some of the requirements for the CPLD design.
The data acquisition engine has the...
VHDL tutorial - A practical example - part 1 - Hardware
In previous posts I described some simple VHDL examples. This time let's try something a little more complex. This is part one of a multiple part article. This is intended to be a detailed description of one of several initial designs that I developed for a client. This design never made it into a product, but a similar design was used and is currently being produced. As a considerable amount of work was put into this effort, I decided to share this design...
Introduction to FPGA Technology
OverviewFPGA stands for Field Programmable Gate Array. An FPGA is an integrated circuit (IC) that can be programmed and configured by the embedded system developer in the field after it has been manufactured. FPGA is a semi-conductor device which is not limited to any pre-defined hardware function; it is rather highly flexible in its functionality and may be configured by the embedded system developer according to his design requirements. FPGAs use pre-built logic blocks and programmable...
Cutting a Path Forward
Introduction
As a newcomer to the community, I thought I would start off by introducing myself, and give a little information about what has drawn me to start working with FPGAs.
My day job is as a professional software developer: Figure out what people want; figure out how to make it happen (if possible); and then wrangle code, databases, networks, and servers into giving the correct responses or actions as necessary.
By night, however, I've been working on my...
FPGA Bloggers Needed - New Reward System
Are you an FPGA expert? If you are an have an interest in sharing your knowledge with the FPGA community, you might be interested in the new reward system for bloggers (see the blogs section here).
The rewards will be based on page impressions, meaning that the more traffic a blog post will get, the faster it will generate rewards for the author.
Basically, a given blog post will generate $25 to the author for every 250 unique pageviews, up to a maximum total reward of $500 per blog post...
State Machine ‘v’ Micro in a FPGA
Designing a system and considering if to have a FPGA in the first place is something a engineer should always consider. However one thing that people look to do is designing a microcontroller on a FPGA and in this post I want to consider why we would do it at all and what would be the real consideration for doing this.
We first look at what's available in the microcontroller world. We have a vast range from tiny 8bit 6 pin devices right the way up to monster 32bit devices. These...
Designing a FPGA Micro Pt1 - Start The Clock
Last time I talked about state machines and micro’s inside FPGAs and why you may want to consider having a micro. So lets say you have decided you want or need a micro in your FPGA design. Where will you start? Well there are lots to pick from but one option is to design your own. So with that in mind I decided to set myself the challenge of doing just that.
Designing a FPGA Micro Pt2 - Clock and Counter build and test.
So last time I looked and talked about designing my own PIC12F509. I concluded by talking shortly about the clock that is used inside the chip. If you have not read this it may be a good time to jump back and read what I have written so far. I’ll be putting links back at the top of every blog from now on to help.State Machine ‘v’ Micro in a FPGADesigning a FPGA Micro Pt1 - Start The ClockOk so this last week I started writing the VHDL code for my PIC core that I’ll be...
Are you kidding me?
If I understand the blog entry [1] correctly, it's saying the industry is ready for high level synthesis (HLS), well almost. The blog states, the higher abstraction level will be achieved via C/C++/SystemC (the C-centric flows). A quote from the blog.
... getting close, and one of the biggest hurdles still to overcome is the skill set -- the combination of hardware design expertise and C++ -- ...
C/C++/SystemC, are you kidding...
How to start in FPGA development? - Simulation software tools
Introduction
This post is related to the first post How to start in FPGA development? - Some tips which aimed to show other options to work on the simulation of your project. In this first approach will be explained some advantages and disadvantages of using Xilinx ISE (+ModelSim) or using ModelSim, Precision and Xilinx ISE. And finally my opinion of which are the ones I...
MyHDL ... MyPWM
The PWM topic appears to be popular lately on the fpgarelated site. This is coincidence, but I typically find the topic of modulating and demodulating signals interesting. For digital systems it is always entertaining to play with PWMs. The following PWM RTL description is quite a bit different than the PWM module described by Anton Babushkin. The module presented here is a minimal PWM engine defined at design time (i.e. not run-time).
As...
MyHDL @EDAPlayground
Trying out MyHDL became a little easier recently. MyHDL is now avaialbe @EDAPlayground. One can experiment with Python/MyHDL verification of HDL modules and implementing complex digital cirucits in MyHDL.
The @EDAPlayground has two main panels. On the left is the testbench and the right the HDL description to be tested.
There are a couple examples...
MyHDL Presentation Examples
The last two years I presented at EELive. The first year as an overview of MyHDL and a strong case why you should be using MyHDL as your hardware description language (HDL) [paper]. The second year was an introduction to three alternative HDLs (alt.hdl), including MyHDL. I also presented at a regional Python conferene: pyohio. At the Python conference I presented...
MyHDL ... MyPWM
The PWM topic appears to be popular lately on the fpgarelated site. This is coincidence, but I typically find the topic of modulating and demodulating signals interesting. For digital systems it is always entertaining to play with PWMs. The following PWM RTL description is quite a bit different than the PWM module described by Anton Babushkin. The module presented here is a minimal PWM engine defined at design time (i.e. not run-time).
As...
Are you kidding me?
If I understand the blog entry [1] correctly, it's saying the industry is ready for high level synthesis (HLS), well almost. The blog states, the higher abstraction level will be achieved via C/C++/SystemC (the C-centric flows). A quote from the blog.
... getting close, and one of the biggest hurdles still to overcome is the skill set -- the combination of hardware design expertise and C++ -- ...
C/C++/SystemC, are you kidding...
Homebrew CPUs: Color Languages
Color Languages
Here on bizarro we program using -- get this – text! Our other senses - hearing, touch, smell, are not used at all. Even our visual perception is greatly underutilized - we just use two-dimensional text on a flat display a foot in front of our eyes.
Color is just beginning to be used, although in a lame syntax coloring way only. Granted, it makes it easier to detect stupid syntax errors such as misspelled keywords. Sadly, color carries zero semantic or...
Designing a FPGA Micro Pt2 - Clock and Counter build and test.
So last time I looked and talked about designing my own PIC12F509. I concluded by talking shortly about the clock that is used inside the chip. If you have not read this it may be a good time to jump back and read what I have written so far. I’ll be putting links back at the top of every blog from now on to help.State Machine ‘v’ Micro in a FPGADesigning a FPGA Micro Pt1 - Start The ClockOk so this last week I started writing the VHDL code for my PIC core that I’ll be...
Choosing an Implementation Approach
What one man can do, another can do!--The Edge (1997) Choose the hill you want to die on.--Common saying attributed to the United States Marine Corps Planning out an FPGA ImplementationIn my first article, I gave a high-level view of the project that brings me into the world of FPGA development. At the end, I tried to break down the areas of development that would be involved, and some of the knowledge and expertise I would probably have to gain in order to make it a...
Tool install for examples
Most of my examples on fpgarelated use MyHDL for the hardware description and another Python package myhdl_tools rhea.build to control the FPGA vendor's software. This means everything is controlled and run from the Python environment.
Install the following to compile the posted examples:
MyHDL package : pip myhdl or myhdl github myhdl_tools : myhdl_tools bitbucket rhea...Cutting a Path Forward
IntroductionAs a newcomer to the community, I thought I would start off by introducing myself, and give a little information about what has drawn me to start working with FPGAs.
My day job is as a professional software developer: Figure out what people want; figure out how to make it happen (if possible); and then wrangle code, databases, networks, and servers into giving the correct responses or actions as necessary.
By night, however, I've been working on my...
Elliptic Curve Digital Signatures
A digital signature is used to prove a message is connected to a specific sender. The sender can not deny they sent that message once signed, and no one can modify the message and maintain the signature. The message itself is not necessarily secret. Certificates of authenticity, digital cash, and software distribution use digital signatures so recipients can verify they are getting what they paid for.
Since messages can be of any length and mathematical algorithms always use fixed...
Grandiose Delusions
Recently on the MyHDL mailing-list there have been discussions about some other immature Python/HDL tools. In these discussion it was mentioned, how over the years, there has not been a strong set of open-source IP developed using MyHDL. For those that might be unfamiliar with the term IP (intellectual property) it is a term widely used in digital hardware to refer to reusable hardware components or blocks.
Many design languages have relied on that first big...
