VGA Output in 7 Slices. Really.
Victor Yurkovsky shows how to generate VGA timing on a Xilinx Spartan3 using clever SRL16 tricks to squeeze the generator into just a few slices. By using 32-bit SRLs for line pulses, two mutually prime SRL lengths as a divide-by-99 timebase, and tapped SRLs to combine HSYNC and HBLANK, the approach achieves accurate-enough horizontal and vertical timing with minimal LUT usage.
How to start in FPGA development? - Simulation software tools
Nuria Orduna lays out a pragmatic approach to FPGA simulation, comparing Xilinx ISE with integrated ModelSim against a three-tool flow with ModelSim and Precision. She explains why independent ModelSim runs and using notepad++ for VHDL can speed debugging, and why Precision and CoreGen conversions can be painful. Read for a compact, practiced workflow to simplify simulation, synthesis, and project organization.
MyHDL FPGA Tutorial II cont. (Echo, Audio Interface)
Christopher Felton walks through connecting an FPGA to a TI AIC23 audio codec using MyHDL, covering SPI register programming and I2S streaming. The post explains how the AIC23 module decodes I2S into parallel samples with a Ts sample-valid strobe and how startup SPI writes configure sample width and rate. You get a simple loopback/echo testbench and practical notes on 16/24/32-bit sample handling.
FPGA Assemblers and Time Machines
Modern FPGA toolchains have turned tinkering into a slog, Victor Yurkovsky recalls the old joy of manual hardware hacking and wants it back. He proposes an assembler-style approach, exemplified by the proposed 'fpgasm', that preserves placement and routing, programs bitstreams in seconds, and makes live probing and rapid iteration practical again. Read this to see why low-level control could revive hands-on FPGA learning.
How to start in FPGA development? - Some tips
Starting from zero, this practical primer walks new FPGA users through the early decisions and habits that make projects work. Nuria Orduna covers how to pick a device, sketch a clear dataflow, prototype in MATLAB or C, organize VHDL entities versus functions, and use ModelSim .do files and testbenches to debug before programming the board. Read it for concise, hands-on starting points.
MyHDL FPGA Tutorial II (Audio Echo)
Christopher Felton demonstrates how to build an FPGA audio echo using MyHDL by storing delayed samples in BRAM and mixing them back with incoming audio. The project shows parameterizable sample rate, sample width, buffer depth, and conversion from MyHDL to Verilog, with a strong emphasis on test-driven verification and simulation-based resource reports. Read on to see how delay, scaling, and BRAM usage affect real-time audio.
An Editor for HDLs
If you prefer Notepad++ over Emacs, Dave Vandenbout shows how to turn it into a capable HDL editor using templates, a Perl package generator, and Emacs run in batch mode for beautification. He covers FingerText snippets for VHDL skeletons, binding a Perl script to auto-create/update package component declarations, and invoking Emacs from a hotkey to format files with one keystroke.
Are you kidding me?
Christopher Felton pushes back on the idea that C/C++/SystemC are the natural path to higher-abstraction FPGA design. He argues hardware designers often do not use C-family languages for modeling and simulation, so choosing C as the HLS lingua franca may be more about tool momentum than suitability. The post urges reconsidering languages with higher abstraction and lower cost of entry for system modeling and HLS.
Designing a FPGA Micro Pt2 - Clock and Counter build and test.
Paul J Clarke continues building his PIC12F509-style soft core by implementing the clock and program counter. He walks through a simple clock_gen.vhd that rotates a four-bit shift register to produce Q1 to Q4 phases, wires it into monpjc_pic_core.vhd for a XuLA target, and adds a 12-bit integer pc_counter that increments on Q1. The post shows simulation testbench results and previews stack and memory work next.
Designing a FPGA Micro Pt1 - Start The Clock
Paul J Clarke takes on cloning a Microchip PIC12F509 inside an FPGA, picking it for its tiny, well-documented architecture. He outlines the core pieces you'll need: 1024×12-bit ROM, 41 bytes of RAM, an ALU, status register, program counter with a two-level stack, GPIO, and the PIC's unusual four-phase internal clock. This post sets the plan and previews the next installment with the first implementation work.
Learning VHDL - Basics
Enrico Garante walks through a compact, hands-on introduction to VHDL and Xilinx ISE, using the affordable Basys2 board. The tutorial explains entity versus architecture, the IEEE.STD_LOGIC_1164 types, and how to write a process with a sensitivity list to implement a simple AND gate. A short ISim video demo shows project creation and simulation so you can verify designs before programming the board.
PicoBlaze - Program RAM Access for an Interactive Monitor
You can give PicoBlaze a live interactive monitor without reconfiguring the FPGA. Victor Yurkovsky walks through using the BRAM's unused port by replacing the assembler template with a dual-ported RAMB16_S18_S18 and exposing maddr, mfromram, mtoram and mwr ports. The post includes IO decoding and a PicoBlaze assembly test to read, write and increment program memory over a serial link.
Elliptic Curve Key Exchange
Elliptic Curve key exchange gives a fresh secret for every session so past messages stay safe even if one key is discovered. This post walks through an ElGamal-style ephemeral exchange and the MQV protocol, showing how MQV mixes static and random keys to provide mutual authentication and forward secrecy. It also explains how MQV can be implemented using only curve operations to save FPGA area and why erasing ephemeral values matters.
Mathematics and Cryptography
Cryptographic math can look intimidating, but this roundup trims it to what FPGA engineers actually need. It groups concise articles on number theory and elliptic curves, focusing on polynomial math over Galois fields, FPGA-friendly inversion and one-clock-cycle techniques, and elliptic-curve key exchange and digital signatures. Read this to learn which subroutines to implement first and how to turn math into Verilog or VHDL.
Elliptic Curve Digital Signatures
Elliptic curve digital signatures deliver compact, strong message authentication by combining a hash of the message with elliptic curve point math. This post walks through the standard sign and verify equations, showing why recomputing a point R' yields the same x coordinate only when the hash matches. It also explains the Nyberg-Rueppel alternative that removes modular inversion and an FPGA-friendly trick of transmitting point D to avoid integer modular arithmetic.
Designing Embedded System with FPGA - 1
Getting an embedded system running on an FPGA is much simpler than it sounds when you use Xilinx EDK and a soft processor. Pragnesh Patel walks through a beginner-friendly approach using the MicroBlaze CPU, drag-and-drop IP cores, and a Spartan-3E starter kit so you can assemble peripherals without deep VHDL knowledge. The post focuses on the EDK base system builder and first setup steps to generate a working design.
MyHDL Resources and Projects
Christopher Felton has pulled together a compact, practical guide to learning and using MyHDL, with the essential manual, Jan Decaluwe's deep dives, presentations, example projects, and active Git/Bitbucket repos. Whether you want a tutorial path, reference reads, or hands-on FPGA projects from simple LEDs to SDR and DSP cores, this curated list points you to vetted resources and real designs to study and reuse.
MyHDL Interface Example
Christopher Felton shows how MyHDL 0.9 interfaces bundle Signals into a single bus object to cut connector clutter and simplify module connections. The post walks through a pedagogical example where button presses drive a memory-mapped BareBoneBus read-modify-write that inverts LEDs, with a TDD-style testbench and notes on converting to Verilog/VHDL and loading the example on supported boards.
MyHDL FPGA Tutorial II cont. (Echo, Audio Interface)
Christopher Felton walks through connecting an FPGA to a TI AIC23 audio codec using MyHDL, covering SPI register programming and I2S streaming. The post explains how the AIC23 module decodes I2S into parallel samples with a Ts sample-valid strobe and how startup SPI writes configure sample width and rate. You get a simple loopback/echo testbench and practical notes on 16/24/32-bit sample handling.
State Machine ‘v’ Micro in a FPGA
A CPU is just a big state machine, but that doesn't mean you always need one in your FPGA. Paul compares hand-written state machines, soft-core CPUs, and standalone microcontrollers, highlighting speed, flexibility, cost, and complexity tradeoffs. Read this if you want a practical way to decide whether to add more state machines, a small soft core, or a separate MCU to your next design.
Mastering Modern FPGA Skills for Engineers
In the rapidly evolving tech industry, engineers must acquire proficiency in modern FPGA skills. These skills empower engineers to optimize designs, minimize resource usage, and efficiently address FPGA design challenges while ensuring functionality, security, and compliance.
The New Forum is LIVE!
After months of hard word, I am very excited to introduce to you the new forum interface.
Here are the key features:
1- Easily add images to a post by drag & dropping the images in the editor
2- Easily attach files to a post by drag & dropping the files in the editor
3- Add latex equations to a post and they will be rendered with Mathjax (tutorial)
4- Add a code snippet and surround the code with
MyHDL synthesis: from browser to FPGA in five seconds
Martin Strubel walks through how modern open-source tooling slashes the pain of converting super-HDLs into FPGA-ready firmware. Instead of long translation chains from MyHDL or nMigen into Verilog or VHDL, yosys and its Python API let you build synthesizeable primitives on the fly, inspect schematics, and emit synthesized Verilog or firmware quickly. The post explains the shift from toolchain friction to fast browser-to-FPGA workflows.
Polynomial Inverse
One of the important steps of computing point addition over elliptic curves is a division of two polynomials.
Three more things you need to know when transitioning from MCUs to FPGAs
Take a look at three more important difference between FPGAs and MCUs: "code reuse" vs templating, metastability and blocking vs. non-blocking operations.
Elliptic Curve Key Exchange
Elliptic Curve key exchange gives a fresh secret for every session so past messages stay safe even if one key is discovered. This post walks through an ElGamal-style ephemeral exchange and the MQV protocol, showing how MQV mixes static and random keys to provide mutual authentication and forward secrecy. It also explains how MQV can be implemented using only curve operations to save FPGA area and why erasing ephemeral values matters.
Elliptic Curve Cryptography - Security Considerations
The security of elliptic curve cryptography is determined by the elliptic curve discrete log problem. This article explains what that means. A comparison with real number logarithm and modular arithmetic gives context for why it is called a log problem.
USB-FPGA : Introduction
Christopher Felton recounts a six-year hobby project to build an open-source USB-FPGA board and its toolchain, from PCB to gateware, firmware, and PC software. He explains why the Cypress FX2 and a Spartan3 were chosen, how the USBP framework supported multiple boards, and why the project’s open-source ambitions didn’t attract the collaboration he expected. Expect practical design and community lessons.
PicoBlaze - Program RAM Access for an Interactive Monitor
You can give PicoBlaze a live interactive monitor without reconfiguring the FPGA. Victor Yurkovsky walks through using the BRAM's unused port by replacing the assembler template with a dual-ported RAMB16_S18_S18 and exposing maddr, mfromram, mtoram and mwr ports. The post includes IO decoding and a PicoBlaze assembly test to read, write and increment program memory over a serial link.
New Discussion Group: DSP & FPGA
I have just created a new discussion group for engineers implementing DSP functions on FPGAs. The creation of this group has been on my todo list for a long time. If you want to join the group, send a blank email to: fpgadsp-subscribe@yahoogroups.com
As usual, it should take a few weeks before there are enough members for interesting discussions to get started.
