MyHDL @EDAPlayground
MyHDL just got easier to try: it's available on EDAPlayground, so you can run Python-based HDL verification directly in the browser. The two-panel editor places the testbench on the left and the HDL under test on the right, with public examples such as a simple strobe and a RAM test ready to copy. Christopher Felton also links a curated resource list to help you get started quickly.
BGA and QFP at Home 1 - A Practical Guide.
It's a myth that BGAs and fine-pitch QFPs can't be soldered at home. Victor Yurkovsky lays out a practical, no-frills approach for hobbyists to design and assemble FPGA boards using 2-layer PCBs, breakout modules, and low-cost reflow methods like toaster ovens or hotplates. The article focuses on manufacturable PCB choices, netlist-driven workflows, and power/decoupling tactics that make high-density parts approachable for amateurs.
Windows XP and Win32 - the Platform of the Future!
Victor Yurkovsky makes the contrarian case that an offline Windows XP VM running Win32 is the most practical platform for modern FPGA development. He explains how Xilinx ISE and related tools often behave far better under XP than on modern Linux distributions, and how VirtualBox fixes USB and GUI headaches. If you maintain FPGA toolchains or write compact C/C++ utilities, this retro setup can save time and frustration.
Introducing the VPCIe framework
Simulating an embedded CPU and FPGA together is painful when PCI Express is in the middle, so Fabien Le Mentec built VPCIe to virtualize that link. VPCIe traps PCIe accesses from a QEMU-hosted CPU and forwards them to a GHDL-driven VHDL simulation using TCP, letting you run unmodified Linux and drivers against your hardware model. The project is open source on GitHub and supports remote or concurrent device simulations.
binary hello world
Christopher Felton walks through two minimalist "binary hello world" examples that make FPGA basics approachable using Python and MyHDL. Attendees wire a button to an LED, add a flip-flop to introduce registers, then implement debouncing and blink-rate control, all compiled with simple Python scripts that drive the FPGA tool flow. Complete source is available on Bitbucket for hands-on experimentation.
Tool install for examples
The post explains the toolchain and installs needed to compile the FPGARelated MyHDL examples. It notes that examples use MyHDL for hardware description and the myhdl_tools/rhea.build Python packages to drive the FPGA vendor tools, so the full flow runs from a Python environment. The author lists required installs: MyHDL (pip or GitHub), myhdl_tools (Bitbucket), the rhea.build automation package, and the FPGA vendor toolchains (Xilinx ISE WebPACK, Altera Quartus, Lattice Diamond). Board-specific programming utilities such as fpgalink and xstools are also required for various development boards. Most examples live in a Bitbucket repository or gist and include a test_and_build_.py script that automates convert, synthesize, map, place-and-route, and bitfile generation. A 2015 changelog notes some tools were deprecated and repository locations were updated.
Shared-multiplier polyphase FIR filter
One multiplier and a dual-port RAM can implement an arbitrary m/n polyphase FIR resampler on an FPGA, Markus Nentwig demonstrates. The post focuses on practical implementation details, including a parametrized Verilog design, pipelined MAC control, and a Matlab testbench for verification. It shows how bank indexing and pipeline delay compensation let you multiplex many coefficient banks efficiently for resource-constrained FPGA designs.
PC and SP for a small CPU
Victor Yurkovsky walks through a compact stack-based CPU idea that tosses the conventional PC register in favor of a return stack living in Xilinx distributed RAM. The clever twist uses the stack memory addressed by SP as the program counter, making calls trivial and keeping the design tiny. The article shows the Verilog stack module and explains the practical tradeoffs of isolating the return stack.
What do Ohio, Python, and FPGAs have in common?
Christopher Felton is bringing MyHDL, Python, and hands-on FPGA work to the free pyohio regional conference on July 27-28. His informal talk introduces programmable hardware to imperative thinkers, contrasts FPGAs with modern computers, and showcases the MyHDL package. The follow-up workshop lets Python programmers edit an example, configure a Xess development board, and see their changes run on real hardware.
How FPGAs work, and why you'll buy one
Yossi Kreinin argues that FPGAs are no longer just programmable gate arrays, they are becoming a mainstream programmable acceleration and I/O platform. The article explains how modern FPGAs pair a sea of LUTs and switch boxes with DSP slices, RAMs, and hard CPUs to deliver massive parallelism, deterministic timing, and surprising energy efficiency, and it includes a readable Verilog convolution example to show how this works in practice.
ESC Boston's Videos are Now Up
In my last blog, I told you about my experience at ESC Boston and the few videos that I was planning to produce and publish. Here they are, please have a look and any feedback (positive or negative) is appreciated.
Short HighlightThis is a very short (one minute) montage of some of the footage that I shot at the show & conference. In future shows, I absolutely need to insert clips here and there of engineers saying a few words about the conference (why they...
VGA Output in 7 Slices. Really.
Victor Yurkovsky shows how to generate VGA timing on a Xilinx Spartan3 using clever SRL16 tricks to squeeze the generator into just a few slices. By using 32-bit SRLs for line pulses, two mutually prime SRL lengths as a divide-by-99 timebase, and tapped SRLs to combine HSYNC and HBLANK, the approach achieves accurate-enough horizontal and vertical timing with minimal LUT usage.
Why I would choose an FPGA development board?
FPGA boards are the smarter choice for hands-on learning and flexible hardware design. Compared with microcontroller dev boards, they let you run many hardware tasks in parallel, reuse the same HDL across different vendors, and even host soft-core microcontrollers inside the fabric. This post walks through those practical advantages and points out modern low-cost boards that make FPGAs accessible for students and engineers.
Feedback Controllers - Making Hardware with Firmware. Part I. Introduction
This first post kicks off a series on using DSP and feedback control with mixed-signal electronics and FPGAs to emulate two-terminal circuits and create low latency controllers. It frames circuit emulation as a feedback problem, highlights latency as the key practical constraint, and outlines the planned evaluation hardware, target devices, and software tools that will be used in later MATLAB/Simulink and FPGA work.
One Clock Cycle Polynomial Math
Error correction codes and cryptographic computations are most easily performed working with GF(2^n)
An Editor for HDLs
If you prefer Notepad++ over Emacs, Dave Vandenbout shows how to turn it into a capable HDL editor using templates, a Perl package generator, and Emacs run in batch mode for beautification. He covers FingerText snippets for VHDL skeletons, binding a Perl script to auto-create/update package component declarations, and invoking Emacs from a hotkey to format files with one keystroke.
PC and SP for a small CPU
Victor Yurkovsky walks through a compact stack-based CPU idea that tosses the conventional PC register in favor of a return stack living in Xilinx distributed RAM. The clever twist uses the stack memory addressed by SP as the program counter, making calls trivial and keeping the design tiny. The article shows the Verilog stack module and explains the practical tradeoffs of isolating the return stack.
MyHDL synthesis: from browser to FPGA in five seconds
Martin Strubel walks through how modern open-source tooling slashes the pain of converting super-HDLs into FPGA-ready firmware. Instead of long translation chains from MyHDL or nMigen into Verilog or VHDL, yosys and its Python API let you build synthesizeable primitives on the fly, inspect schematics, and emit synthesized Verilog or firmware quickly. The post explains the shift from toolchain friction to fast browser-to-FPGA workflows.
Embedded World 2018 - The Interviews
Stephane Boucher brought video gear to Embedded World 2018 and teamed up with Jacob Beningo to capture concise vendor interviews that focus on real product news. The videos showcase Percepio's new Tracealyzer with a drone demo, Intrinsic ID's method for creating device-unique IDs from manufacturing variations, and SEGGER's broader toolset including embOS now certified by TÜV SÜD. Watch for short demos and expert explanations.
Developing FPGA-DSP IP with Python
Designing FPGA-DSP IP entirely in Python is practical and productive, as Christopher Felton demonstrates using MyHDL. He shows how numpy and scipy handle the signal design while a SIIR class generates RTL, enables side-by-side floating-point and HDL simulation, and converts to Verilog for synthesis. The post includes Xilinx XC3S500E resource results and a link to the SIIR source on BitBucket, making it easy to try the workflow.
Feedback Controllers - Making Hardware with Firmware. Part 3. Sampled Data Aspects
This article digs into practical sampled-data issues you must address when building feedback controllers for circuit emulation. It highlights a common MATLAB versus Simulink discrepancy caused by DAC holding, explains why FOH (ramp-invariant) c2d conversion matters, and surveys latency, bit depth, filter and precision trade-offs. It also lists candidate ADCs, DACs and FPGAs used in a real evaluation platform to guide hardware choices.
Feedback Controllers - Making Hardware with Firmware. Part 4. Engineering of Evaluation Hardware
Following on from the previous abstract descriptions of an arbitrary circuit emulation application for low-latency feedback controllers, we now come to some aspects in the hardware engineering of an evaluation design from concept to first power-up. In due course a complete specification along with application examples will be maintained on the project website.- Part 1: Introduction
- Part 2:...
Use a Simple Microprogram Controller (MPC) to Speed Development of Complex Microprogrammed State Machines
The article presents a synthesizable Verilog microprogram controller (MPC) modeled on the Fairchild F9408 that simplifies development of complex microprogrammed state machines. It explains desirable MPC features — a loadable program counter for sequential and non-sequential execution, conditional and multi-way branching, and a microsubroutine stack — and then provides a working HDL implementation (F9408A_MPC). The module is parameterized for microprogram address width, supports a 4-level LIFO return stack, 8-way multiway branch via an external selector, pipelined or non-pipelined operation, and registered test inputs for conditional branches. The article includes the full Verilog source and discusses practical uses of the MPC in designs from protocol controllers to a 65C02 microprocessor reimplementation.
An absolute position encoder VHDL core
In this article, Fabien Le Mentec explains how to implement a unique VHDL core addressing absolute position encoder interfaces. He reviews existing instruments in use or being developed and considers their specific requirements. He also looks for details in current implementations and considers the projects to come so that the implementation can be designed to be extensible. The VHDL core dubbed absenc features both ENDAT, BISS and SSI interface. Due to its architecture, new interfaces are easily added. Also, the 3 interfaces can be enabled at synthesis while 1 is selected at runtime. As much as possible, resources common to the different interfaces are shared (counters, comparators…).
Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop
This article demonstrates combining DSP and feedback-control on an Intel Cyclone floating-point FPGA to build low-latency closed-loop circuit emulators and controllers. Using a single floating-point biquad at 1.6 Msps, an IFFT multi-tone 4.096 ms capture for wideband measurement, and MATLAB references for verification, the author achieves sub-nanosecond timing insight and applies DSP phase compensation to cancel about 100 pF of PCB parasitics.
FPGA Assemblers and Time Machines
Modern FPGA toolchains have turned tinkering into a slog, Victor Yurkovsky recalls the old joy of manual hardware hacking and wants it back. He proposes an assembler-style approach, exemplified by the proposed 'fpgasm', that preserves placement and routing, programs bitstreams in seconds, and makes live probing and rapid iteration practical again. Read this to see why low-level control could revive hands-on FPGA learning.
Jumping from MCUs to FPGAs - 5 things you need to know
Are you a microcontroller expert beckoned by the siren song of the FPGA? Not long ago, that was me. FPGA-expert friends of mine regularly extolled the virtues of these mysterious components and I wanted in. When I made the leap, I found a world seemingly very familiar, but in reality, vastly different. I found that my years of C programming and microcontroller use often gave pre preconceived interpretations of FPGA resource material which resulted in eye-roll class mistakes in my code. I’ve gleaned five things of vital importance to help you make that transition faster than I did.
Designing Embedded System with FPGA - 1
Getting an embedded system running on an FPGA is much simpler than it sounds when you use Xilinx EDK and a soft processor. Pragnesh Patel walks through a beginner-friendly approach using the MicroBlaze CPU, drag-and-drop IP cores, and a Spartan-3E starter kit so you can assemble peripherals without deep VHDL knowledge. The post focuses on the EDK base system builder and first setup steps to generate a working design.
Helping New Bloggers to Break the Ice: A New Ipad Pro for the Author with the Best Article!
Breaking the ice can be tough. Over the years, many individuals have asked to be given access to the blogging interface only to never post an article.
New book on Elliptic Curve Cryptography
New book on Elliptic Curve Cryptography now online. Deep discount for early purchase. Will really appreciate comments on how to improve the book because physical printing won't happen for a few more months. Check it out here: http://mng.bz/D9NA
