MyHDL FPGA Tutorial II (Audio Echo)

Christopher Felton July 18, 2012

This tutorial will walk through an audio echo that can be implemented on an FPGA development board.  This tutorial is quite a bit more involved than the previous MyHDL FPGA tutorial.  This project will require an FPGA board with an audio codec and the interface logic to the audio codec.

Review the Previous Tutorial

The previous MyHDL FPGA tutorial I posted a strobing LED on an FPGA board.  In that tutorial we introduced the basics of a MyHDL module....

An Editor for HDLs

Dave Vandenbout July 17, 201211 comments

Unless you're still living in the '90s and using schematics, your FPGA designs are entered into text files as VHDL or Verilog source. Which, of course, implies you're using some form of text editor. Now, right after brace placement in C, the choice of an editor is the topic most likely to incite a nerd civil war (it's a bike-shed issue). I won't attempt to influence your choice because it really makes no difference to me. But if you are using the same editor I do, then maybe I can help you...

Are you kidding me?

Christopher Felton July 1, 2012

If I understand the blog entry [1] correctly, it's saying the industry is ready for high level synthesis (HLS), well almost.  The blog states, the higher abstraction level will be achieved via C/C++/SystemC (the C-centric flows).  A quote from the blog.

... getting close, and one of the biggest hurdles still to overcome is the skill set -- the combination of hardware design expertise and C++ -- ...

C/C++/SystemC, are you kidding...

Designing a FPGA Micro Pt2 - Clock and Counter build and test.

Paul J Clarke June 26, 20121 comment

So last time I looked and talked about designing my own PIC12F509. I concluded by talking shortly about the clock that is used inside the chip. If you have not read this it may be a good time to jump back and read what I have written so far. I’ll be putting links back at the top of every blog from now on to help.State Machine ‘v’ Micro in a FPGADesigning a FPGA Micro Pt1 - Start The ClockOk so this last week I started writing the VHDL code for my PIC core that I’ll be...

Designing a FPGA Micro Pt1 - Start The Clock

Paul J Clarke May 22, 2012

Last time I talked about state machines and micro’s inside FPGAs and why you may want to consider having a micro. So lets say you have decided you want or need a micro in your FPGA design. Where will you start? Well there are lots to pick from but one option is to design your own. So with that in mind I decided to set myself the challenge of doing just that.


Grandiose Delusions

Christopher Felton May 3, 2012

Recently on the MyHDL mailing-list there have been discussions about some other immature Python/HDL tools.  In these discussion it was mentioned, how over the years, there has not been a strong set of open-source IP developed using MyHDL.  For those that might be unfamiliar with the term IP (intellectual property) it is a term widely used in digital hardware to refer to reusable hardware components or blocks.

Many design languages have relied on that first big...

State Machine ‘v’ Micro in a FPGA

Paul J Clarke April 23, 2012

Designing a system and considering if to have a FPGA in the first place is something a engineer should always consider. However one thing that people look to do is designing a microcontroller on a FPGA and in this post I want to consider why we would do it at all and what would be the real consideration for doing this.

We first look at what's available in the microcontroller world. We have a vast range from tiny 8bit 6 pin devices right the way up to monster 32bit devices. These...

My VHDL <= monpjc; Journey

Paul J Clarke March 18, 20121 comment

I always like to start my first blog on a website with a bit of a introduction as to who I am and what I’ll be writting about. I feel this gives you the reader a opportunity to see where I’m coming from and understand a little of my point of view. So when I was asked to come and start blogging on FPGARelated I wondered what I should say. So for my first blog its all about how me, aka monpjc, and how I got into VHDL.

It started a long time ago when I was working for a...

MyHDL FPGA Tutorial I (LED Strobe)

Christopher Felton January 31, 20126 comments

Last updated 05-Nov-2015


From many perspectives the latest FPGA offerings from 'X' and 'A' are large devices - mucho programmable logic resources.  Even the devices that one can get for sub \$10 are relatively large.  Because of the size of these FPGAs they are implemented using an HDL.  To manually configure each circuit would be a long and tedious task.  It is not feasible to program an FPGA by manually defining the logic for each LUT and manually...

Oscilloscope Dreams

Jason Sachs January 14, 20125 comments

My coworkers and I recently needed a new oscilloscope. I thought I would share some of the features I look for when purchasing one.

When I was in college in the early 1990's, our oscilloscopes looked like this:

Now the cathode ray tubes have almost all been replaced by digital storage scopes with color LCD screens, and they look like these:

Oscilloscopes are basically just fancy expensive boxes for graphing voltage vs. time. They span a wide range of features and prices:...

One Clock Cycle Polynomial Math

Mike November 20, 201514 comments

Error correction codes and cryptographic computations are most easily performed working with $GF(2^n)$  polynomials.  By using very special values of $n$ we can build circuits which multiply and square in one clock cycle on an FPGA. These circuits come about by flipping back and forth between a standard polynomial basis and a normal basis representation of elements in $GF(2^n)$.

A normal basis is yet another form of polynomial but instead of adding powers of $\beta$ we add...

Part 11. Using -ve Latency DSP to Cancel Unwanted Delays in Sampled-Data Filters/Controllers

Steve Maslen June 18, 201917 comments
This final article in the series will look at -ve latency DSP and how it can be used to cancel the unwanted delays in sampled-data systems due to such factors as Nyquist filtering, ADC acquisition, DSP/FPGA algorithm computation time, DAC reconstruction and circuit propagation delays.

Some applications demand zero-latency or zero unwanted latency signal processing. Negative latency DSP may sound like the stuff of science fiction or broken physics but the arrangement as...

Elliptic Curve Key Exchange

Mike December 3, 2015

Elliptic Curve Cryptography is used to create a Public Key system that allows two people (or computers) to exchange public data so that both sides know a secret that no one else can find in a reasonable time.  The simplest method uses a fixed public key for each person.  Once cracked, every message ever sent with that key is open.  More advanced key exchange systems have "perfect forward secrecy" which means that even if one message key is cracked, no other message will...

Feedback Controllers - Making Hardware with Firmware. Part 6. Self-Calibration Related.

Steve Maslen December 3, 20177 comments

This article will consider the engineering of a self-calibration & self-test capability to enable the project hardware to be configured and its basic performance evaluated and verified, ready for the development of the low-latency controller DSP firmware and closed-loop applications. Performance specifications will be documented in due course, on the project website here.

  • Part 6: Self-Calibration, Measurements and Signalling (this part)
  • Part 5:

Feedback Controllers - Making Hardware with Firmware. Part 5. Some FPGA Aspects.

Steve Maslen November 14, 2017
This part of the on-going series of articles looks at a variety of aspects concerning the FPGA device which provides the high-speed maths capability for the low-latency controller and the arbitrary circuit generator application. In due course a complete specification along with  application  examples will be maintained on the project website here.

New Discussion Group: DSP & FPGA

Stephane Boucher September 11, 20078 comments

I have just created a new discussion group for engineers implementing DSP functions on FPGAs. The creation of this group has been on my todo list for a long time. If you want to join the group, send a blank email to:

As usual, it should take a few weeks before there are enough members for interesting discussions to get started.

Polynomial Inverse

Mike November 23, 20152 comments

One of the important steps of computing point addition over elliptic curves is a division of two polynomials.  When working in $GF(2^n)$ we don't have large enough powers to actually do a division, so we compute the inverse of the denominator and then multiply.  This is usually done using Euclid's method, but if squaring and multiplying are fast we can take advantage of these operations and compute the multiplicative inverse in just a few steps.

The first time I ran across this...

The New Forum is LIVE!

Stephane Boucher February 18, 20161 comment

After months of hard word, I am very excited to introduce to you the new forum interface.  

Here are the key features:

1- Easily add images to a post by drag & dropping the images in the editor

2- Easily attach files to a post by drag & dropping the files in the editor

3- Add latex equations to a post and they will be rendered with Mathjax (tutorial)

4- Add a code snippet and surround the code with

Launch of

Stephane Boucher February 21, 2019

With the upcoming Embedded Word just around the corner, I am very excited to launch the platform.  

This is where you will find the schedule for all the live broadcasts that I will be doing from Embedded World next week.  Please note that the schedule will be evolving constantly, even during the show, so I suggest your refresh the page often.  For instance, I am still unsure if I will be able to do the 'opening of the doors' broadcast as...


Christopher Felton June 3, 20136 comments

The PWM topic appears to be popular lately on the fpgarelated site.  This is coincidence, but I typically find the topic of modulating and demodulating signals interesting.  For digital systems it is always entertaining to play with PWMs.  The following PWM RTL description is quite a bit different than the PWM module described by Anton Babushkin.  The module presented here is a minimal PWM engine defined at design time (i.e. not run-time).