FPGARelated.com

PicoBlaze - Program RAM Access for an Interactive Monitor

Victor Yurkovsky June 14, 20132 comments

I have a confession to make: I love PicoBlaze!  There are many reasons to love it.  It is a tiny CPU (96 Spartan3 slices or 26 Spartan6 slices plus a BRAM).  It is simple.  It is bug-free.  It's pretty fast.  It can reduce the size and the complexity of your design - instead of debugging a big state machine, just throw one (or more) of these in.  Add a serial output and you can debug your fpga from inside out!However, there are a few problems.  The...


MyHDL ... MyPWM

Christopher Felton June 3, 20136 comments

The PWM topic appears to be popular lately on the fpgarelated site.  This is coincidence, but I typically find the topic of modulating and demodulating signals interesting.  For digital systems it is always entertaining to play with PWMs.  The following PWM RTL description is quite a bit different than the PWM module described by Anton Babushkin.  The module presented here is a minimal PWM engine defined at design time (i.e. not run-time).  

As...


StrangeCPU #4. Microcode

Victor Yurkovsky May 13, 20137 comments
Summary:

Sliding windows containing runs of microcode.

Table of Contents:

StrangeCPU #3. Instruction Slides - The Strangest CPU Yet!

Victor Yurkovsky March 18, 201311 comments
Summary:

Decoding instructions with a Sliding Window system.  0-Bit Sliding Register Windows.

Table of Contents:

StrangeCPU #2. Sliding Window Token Machines

Victor Yurkovsky March 5, 201313 comments
Summary:

An in-depth exploration of Sliding Window Token Machines; ARM notes.

Table of Contents:

StrangeCPU #1. A new CPU

Victor Yurkovsky February 24, 20136 comments

Summary: In this multi-part series I will share with you a design, implementation notes and code for a slightly different kind of a CPU featuring a novel token machine that resolves an 8-bit token to pretty much any address in a 32-bit or even 64-bit address space, using not much more than an adder.

Table of Contents:
  • Part 1: A new CPU - technology review, re-examination of the premises;  StrangeCPU concepts; x86 notes.

MyHDL Resources and Projects

Christopher Felton December 9, 20122 comments

Last updated 07-Nov-2017

MyHDL Resources

If you want to dive into MyHDL (digital hardware description in Python) there are many resources available.  Below is a list of MyHDL resources, including some of the past blogs here on fpgarelated.

The MyHDL manual is a great (probably the best) place to get started.

The manual is an in-depth introduction to MyHDL.  The concepts are well explained and there are examples to test while working through the...


Two jobs

Stephane Boucher December 5, 201223 comments

For those of you following closely embeddedrelated and the other related sites, you might have noticed that I have been less active for the last couple of months, and I will use this blog post to explain why. The main reason is that I got myself involved into a project that ended up using a better part of my cpu than I originally thought it would.

edit - video of the event:

I currently have two jobs: one as an electrical/dsp engineer recycled as a web publisher and the other...


VGA Output in 7 Slices. Really.

Victor Yurkovsky September 25, 20122 comments

Ridiculous? Read on - I will show you how to generate VGA timing in seven XilinxR Spartan3R slices.Some time ago I needed to output video to a VGA monitor for my Apple ][ FPGA clone.  Obviously (I thought), VGA's been done before and all I had to do was find some Verilog code and drop it into my design.  As is often the case (with me anyway), the task proved to be very different from my imagined 'couple of hours to integrate the IP'.I found some example code for my board.  I...


Feedback Controllers - Making Hardware with Firmware. Part 8. Control Loop Test-bed

Steve Maslen March 21, 2018

This part in the series will consider the signals, measurements, analyses and configurations for testing high-speed low-latency feedback loops and their controllers. Along with basic test signals, a versatile IFFT signal generation scheme will be discussed and implemented. A simple controller under test will be constructed to demonstrate the analysis principles in preparation for the design and evaluation of specific controllers and closed-loop applications.

Additional design...

Square root in fixed point VHDL

Jari Honkanen October 10, 2023

In this blog we will design and implement a fixed point square root function in VHDL. The algorithm is based on the recursive Newton Raphson inverse square root algorithm and the implementation offers parametrizable pipeline depth, word length and the algorithm is built with VHDL records and procedures for easy use.


Feedback Controllers - Making Hardware with Firmware. Part 6. Self-Calibration Related.

Steve Maslen December 3, 20177 comments

This article will consider the engineering of a self-calibration & self-test capability to enable the project hardware to be configured and its basic performance evaluated and verified, ready for the development of the low-latency controller DSP firmware and closed-loop applications. Performance specifications will be documented in due course, on the project website here.

  • Part 6: Self-Calibration, Measurements and Signalling (this part)
  • Part 5:

Ancient History

Mike January 18, 201612 comments

The other day I was downloading an IDE for a new (to me) OS.  When I went to compile some sample code, it failed.  I went onto a forum, where I was told "if you read the release notes you'd know that the peripheral libraries are in a legacy download".  Well damn!  Looking back at my previous versions I realized I must have done that and forgotten about it.  Everything changes, and keeping up with it takes time and effort.

When I first started with microprocessors we...


Mathematics and Cryptography

Mike December 14, 20153 comments

The mathematics of number theory and elliptic curves can take a life time to learn because they are very deep subjects.  As engineers we don't have time to earn PhD's in math along with all the things we have to learn just to make communications systems work.  However, a little learning can go a long way to helping make our communications systems secure - we don't need to know everything. The following articles are broken down into two realms, number theory and elliptic...


PicoBlaze - Program RAM Access for an Interactive Monitor

Victor Yurkovsky June 14, 20132 comments

I have a confession to make: I love PicoBlaze!  There are many reasons to love it.  It is a tiny CPU (96 Spartan3 slices or 26 Spartan6 slices plus a BRAM).  It is simple.  It is bug-free.  It's pretty fast.  It can reduce the size and the complexity of your design - instead of debugging a big state machine, just throw one (or more) of these in.  Add a serial output and you can debug your fpga from inside out!However, there are a few problems.  The...


Designing Embedded Systems with FPGA-2

Pragnesh Patel November 13, 200710 comments

In last part, we created hardware design of basic system. The next step is to generate (compile) hardware design. Compiled hardware design is known as bit-stream andstored in *.bit file. To compile hardware, use hardware->generate hardware tab. The complete hardware design generation takes several seconds to several minutes depending on computer speed and design complexity. In back ground, the whole design process involves many different steps including synthesis, placement, routing and...


Why I would choose an FPGA development board?

Pablo Trujillo November 17, 20221 comment

Some years ago, when I went to the University, I bought some development boards based on different microcontrollers, and I remember that, although development boards were not expensive, I had to add to the price of the board, the shipping costs and the taxes, which were more than the 50% of the price of the board, but there are no option if I wanted to test that microcontroller. When I wanted to test some other feature, I had to buy a different board, for example, if I wanted to design some...


MyHDL Interface Example

Christopher Felton January 18, 20142 comments
MyHDL Interfaces Example

With the next release of MyHDL, version 0.9, conversion of interfaces will be supported.  In this context an interface is any object with a Signal attribute.  This can be used to simplify connection between modules and port definitions.  For example, if I want to define a simple memory-map bus, the Signals for the bus can be defined as follows:

class BareBoneBus: def __init__(self): self.wr = Signal(False) self.rd =...