## MyHDL ... MyPWM

The PWM topic appears to be popular lately on the fpgarelated site.  This is coincidence, but I typically find the topic of modulating and demodulating signals interesting.  For digital systems it is always entertaining to play with PWMs.  The following PWM RTL description is quite a bit different than the PWM module described by Anton Babushkin.  The module presented here is a minimal PWM engine defined at design time (i.e. not run-time).

As...

## StrangeCPU #4. Microcode

Summary:

Sliding windows containing runs of microcode.

## Yet another PWM

April 6, 20131 comment

## StrangeCPU #3. Instruction Slides - The Strangest CPU Yet!

Summary:

Decoding instructions with a Sliding Window system.  0-Bit Sliding Register Windows.

## StrangeCPU #2. Sliding Window Token Machines

Summary:

An in-depth exploration of Sliding Window Token Machines; ARM notes.

## StrangeCPU #1. A new CPU

Summary: In this multi-part series I will share with you a design, implementation notes and code for a slightly different kind of a CPU featuring a novel token machine that resolves an 8-bit token to pretty much any address in a 32-bit or even 64-bit address space, using not much more than an adder.

• Part 1: A new CPU - technology review, re-examination of the premises;  StrangeCPU concepts; x86 notes.

## MyHDL Resources and Projects

Last updated 07-Nov-2017

MyHDL Resources

If you want to dive into MyHDL (digital hardware description in Python) there are many resources available.  Below is a list of MyHDL resources, including some of the past blogs here on fpgarelated.

The MyHDL manual is a great (probably the best) place to get started.

The manual is an in-depth introduction to MyHDL.  The concepts are well explained and there are examples to test while working through the...

## Two jobs

For those of you following closely embeddedrelated and the other related sites, you might have noticed that I have been less active for the last couple of months, and I will use this blog post to explain why. The main reason is that I got myself involved into a project that ended up using a better part of my cpu than I originally thought it would.

edit - video of the event:

I currently have two jobs: one as an electrical/dsp engineer recycled as a web publisher and the other...

## VGA Output in 7 Slices. Really.

Ridiculous? Read on - I will show you how to generate VGA timing in seven XilinxR Spartan3R slices.Some time ago I needed to output video to a VGA monitor for my Apple ][ FPGA clone.  Obviously (I thought), VGA's been done before and all I had to do was find some Verilog code and drop it into my design.  As is often the case (with me anyway), the task proved to be very different from my imagined 'couple of hours to integrate the IP'.I found some example code for my board.  I...

## How to start in FPGA development? - Simulation software tools

Introduction

This post is related to the first post How to start in FPGA development? - Some tips which aimed to show other options to work on the simulation of your project. In this first approach will be explained some advantages and disadvantages of using Xilinx ISE (+ModelSim) or using ModelSim, Precision and Xilinx ISE. And finally my opinion of which are the ones I...

## Helping New Bloggers to Break the Ice: A New Ipad Pro for the Author with the Best Article!

November 9, 2015

Breaking the ice can be tough.  Over the years, many individuals have asked to be given access to the blogging interface only to never post an article.  Maybe they underestimated the time it takes to write a decent article, or maybe they got cold feet. I don't blame or judge them at all - how many times in my life have I had the intention to do something but didn't follow through?  Once, maybe twice 😉 (don't worry if you don't...

## Computing Fixed-Point Square Roots and Their Reciprocals Using Goldschmidt Algorithm

Introduction

A well known algorithm for computing square roots by iteration is provided by the Newton-Raphson Algorithm. The algorithm determines the square root using iteration until the root has been determined to some user-defined level of accuracy. The method is easily derived. First, describe a number in terms of its square root:

$$a = y ^ {2} ,$$

where $y = \sqrt{a}$. The value of the $\sqrt{a}$ can be written as $y = y_0 + \epsilon$, where $y_0$ is the value of the square root and...

## Feedback Controllers - Making Hardware with Firmware. Part 4. Engineering of Evaluation Hardware

October 10, 2017
Following on from the previous abstract descriptions of an arbitrary circuit emulation application for low-latency feedback controllers, we now come to some aspects in the hardware engineering of an evaluation design from concept to first power-up. In due course a complete specification along with  application  examples will be maintained on the project website.

## Feedback Controllers - Making Hardware with Firmware. Part 3. Sampled Data Aspects

September 9, 2017
Some Design and Simulation Considerations for Sampled-Data Controllers

This article will continue to look at some aspects of the controllers and electronics needed to create emulated physical circuits with real-world connectivity and will look at the issues that arise in sampled-data controllers compared to continuous-domain controllers. As such, is not intended as an introduction to sampled-data systems.

## Yet another PWM

April 6, 20131 comment

## Feedback Controllers - Making Hardware with Firmware. Part 8. Control Loop Test-bed

March 21, 2018

This part in the series will consider the signals, measurements, analyses and configurations for testing high-speed low-latency feedback loops and their controllers. Along with basic test signals, a versatile IFFT signal generation scheme will be discussed and implemented. A simple controller under test will be constructed to demonstrate the analysis principles in preparation for the design and evaluation of specific controllers and closed-loop applications.

## The DSP Online Conference - Right Around the Corner!

September 20, 2020

It is Sunday night as I write this blog post with a few days to go before the virtual doors of the very first DSP Online Conference open..

It all started with a post in the DSPRelated forum about three months ago.  We had just had a blast running the 2020 Embedded Online Conference and we thought it could be fun to organize a smaller event dedicated to the DSP community.  So my goal with the post in the forum was to see if...

## Designing Embedded Systems with FPGA-2

In last part, we created hardware design of basic system. The next step is to generate (compile) hardware design. Compiled hardware design is known as bit-stream andstored in *.bit file. To compile hardware, use hardware->generate hardware tab. The complete hardware design generation takes several seconds to several minutes depending on computer speed and design complexity. In back ground, the whole design process involves many different steps including synthesis, placement, routing and...