Shared-multiplier polyphase FIR filter

Markus Nentwig July 31, 20135 comments

Keywords: FPGA, interpolating decimating FIR filter, sample rate conversion, shared multiplexed pipelined multiplier

Discussion, working code (parametrized Verilog) and Matlab reference design for a FIR polyphase resampler with arbitrary interpolation and decimation ratio, mapped to one multiplier and RAM.

Introduction

A polyphase filter can be as straightforward as multirate DSP ever gets, if it doesn't turn into a semi-deterministic, three-legged little dance between input, output and...


PC and SP for a small CPU

Victor Yurkovsky July 23, 2013

Ok, let's make a small stack-based CPU.

I will start where the rubber meets the road - the PC/stack subsystem that I like referring to as the 'legs'. As usual, I will present a design with a twist.

Not having a large design team, deadlines and million-dollar fab runs when designing CPUs creates a truly different environment. I can actually sit at the kitchen table and doodle around with CPU designs to my heart's content. I can try really ridiculous approaches, and work without a...


What do Ohio, Python, and FPGAs have in common?

Christopher Felton July 23, 2013

Anyone in the Columbus Ohio area in the United States this upcoming weekend (7/27 and 7/28) should stop by the @pyohio conference.  This is a *FREE* regional python conference.  I will be giving a talk at the end of the day Sunday, discussing MyHDL, FPGAs, and a hands-on workshop following the presentation.

The talk will focus on introducing programmable hardware to "imperative thinkers".  Anyone curious about FPGAs, Python, or familiar with FPGAs or embedded...


How FPGAs work, and why you'll buy one

Yossi Kreinin June 20, 201314 comments

Today, pretty much everyone has a CPU, a DSP and a GPU, buried somewhere in their PC, phone, car, etc. Most don't know or care that they bought any of these, but they did.

Will everyone, at some future point, also buy an FPGA? The market size of FPGAs today is about 1% of the annual global semiconductor sales (~$3B vs ~$300B). Will FPGA eventually...


Learning VHDL - Basics

Enrico Garante June 15, 20135 comments

Since FPGA are becoming more accessible to the hobbyist, learning how to use them can be really useful for certain applications, like DSP and video generation; moreover, engineers that are able to code in VHDL/Verilog are always requested on the job market.

In this tutorial I will cover the basics of Xilinx ISE and VHDL. I willl base my code on the Basys2 board from Digilent: it is really cheap (especially for students) and has a lot of features on board, as you can see from the picture...


PicoBlaze - Program RAM Access for an Interactive Monitor

Victor Yurkovsky June 14, 20132 comments

I have a confession to make: I love PicoBlaze!  There are many reasons to love it.  It is a tiny CPU (96 Spartan3 slices or 26 Spartan6 slices plus a BRAM).  It is simple.  It is bug-free.  It's pretty fast.  It can reduce the size and the complexity of your design - instead of debugging a big state machine, just throw one (or more) of these in.  Add a serial output and you can debug your fpga from inside out!However, there are a few problems.  The...


MyHDL ... MyPWM

Christopher Felton June 3, 20136 comments

The PWM topic appears to be popular lately on the fpgarelated site.  This is coincidence, but I typically find the topic of modulating and demodulating signals interesting.  For digital systems it is always entertaining to play with PWMs.  The following PWM RTL description is quite a bit different than the PWM module described by Anton Babushkin.  The module presented here is a minimal PWM engine defined at design time (i.e. not run-time).  

As...


StrangeCPU #4. Microcode

Victor Yurkovsky May 13, 20137 comments
Summary:

Sliding windows containing runs of microcode.

Table of Contents:

StrangeCPU #3. Instruction Slides - The Strangest CPU Yet!

Victor Yurkovsky March 18, 201311 comments
Summary:

Decoding instructions with a Sliding Window system.  0-Bit Sliding Register Windows.

Table of Contents:

ESC Boston's Videos are Now Up

Stephane Boucher June 5, 2017

In my last blog, I told you about my experience at ESC Boston and the few videos that I was planning to produce and publish.  Here they are, please have a look and any feedback (positive or negative) is appreciated. 

Short Highlight

This is a very short (one minute) montage of some of the footage that I shot at the show & conference.  In future shows, I absolutely need to insert clips here and there of engineers saying a few words about the conference (why they...


Feedback Controllers - Making Hardware with Firmware. Part 7. Turbo-charged DSP Oscillators

Steve Maslen January 5, 20187 comments
This article will look at some DSP Sine-wave oscillators and will show how an FPGA with limited floating-point performance due to latency, can be persuaded to produce much higher sample-rate sine-waves of high quality. 

Comparisons will be made between implementations on Intel Cyclone V and Cyclone 10 GX FPGAs. An Intel numerically controlled oscillator


Feedback Controllers - Making Hardware with Firmware. Part 2. Ideal Model Examples

Steve Maslen August 24, 2017
Developing and Validating Simulation Models

This article will describe models for simulating the systems and controllers for the hardware emulation application described in Part 1 of the series.


Tools of the Trade: reading PDFs (and keeping bookmarks)

Victor Yurkovsky July 7, 20155 comments

In this article I will take a look at the wonderful MuPDF viewer and present a small modification that saves bookmarks alongside the pdf files, making it infinitely more useful.

Some days I sit down to work and wonder how anything ever gets done. A simple example.  When I work on an FPGA design, I wind up with 3 or 4 screens full of documentation, generally in PDF format.  There are the Xilinx manuals, the various tool manuals, language reference manuals, you name it.  While...


Designing Embedded Systems with FPGA-2

Pragnesh Patel November 13, 200710 comments

In last part, we created hardware design of basic system. The next step is to generate (compile) hardware design. Compiled hardware design is known as bit-stream andstored in *.bit file. To compile hardware, use hardware->generate hardware tab. The complete hardware design generation takes several seconds to several minutes depending on computer speed and design complexity. In back ground, the whole design process involves many different steps including synthesis, placement, routing and...


Helping New Bloggers to Break the Ice: A New Ipad Pro for the Author with the Best Article!

Stephane Boucher November 9, 2015

Breaking the ice can be tough.  Over the years, many individuals have asked to be given access to the blogging interface only to never post an article.  Maybe they underestimated the time it takes to write a decent article, or maybe they got cold feet. I don't blame or judge them at all - how many times in my life have I had the intention to do something but didn't follow through?  Once, maybe twice 😉 (don't worry if you don't...


Mathematics and Cryptography

Mike December 14, 20153 comments

The mathematics of number theory and elliptic curves can take a life time to learn because they are very deep subjects.  As engineers we don't have time to earn PhD's in math along with all the things we have to learn just to make communications systems work.  However, a little learning can go a long way to helping make our communications systems secure - we don't need to know everything. The following articles are broken down into two realms, number theory and elliptic...


Project introduction: Digital Filter Blocks in MyHDL and their integration in pyFDA

Sriyash Caculo May 25, 20184 comments

Hi everyone! After a lot of hesitation and several failed attempts, I have finally entered the world of blogging. A little about myself : My name is Sriyash Caculo and I’m a third year undergrad student at BITS Pilani K.K. Birla Goa Campus  pursuing a major in Electronics and Instrumentation engineering. Being an electronics engineer, I developed an interest in Digital Signal Processing and its implementation on hardware.

This blog-post is the first of many to come for the...


Designing a FPGA Micro Pt1 - Start The Clock

Paul J Clarke May 22, 2012

Last time I talked about state machines and micro’s inside FPGAs and why you may want to consider having a micro. So lets say you have decided you want or need a micro in your FPGA design. Where will you start? Well there are lots to pick from but one option is to design your own. So with that in mind I decided to set myself the challenge of doing just that.