## Windows XP and Win32 - the Platform of the Future!

October 6, 20132 comments

Over the past decade I often wondered why anyone uses Windows.  It's just so... proprietary.  And pedestrian.  As I grew up my OS of choice went nothing to CPM to DOS (on Apple ][), GEM on Atari ST,  MS-DOS, DOS extenders, Mac OS, Windows NT, Windows XP, Linux...  Now, I again find myself a fan of Windows XP, the platform of the future.  (I am still a fan of bare metal, of course).Maybe I am not totally serious, but I, a self-proclaimed freedom lover and...

## Introducing the VPCIe framework

August 31, 20133 comments
Introduction

My daily work involves platforms featuring an embedded CPU communcating with a FPGA device over a PCI Express link (PCIe for short). The main purpose of this link is for the CPU to convey configuration, control, and status commands to hardware slaves implemented in the FPGA. For data intensive applications (2D XRay detector readout backend), this link can also be used as a DMA channel to transfer data from the FPGA to the CPU memory. Finally, a slave can interrupt the CPU using...

## binary hello world

August 3, 20132 comments
Python + Ohio + MyHDL + FPGA

Recently I had the opportunity to coordinate a hands-on programmable hardware (FPGA) workshop (open-space) at a regional Python conference - @pyohio. The workshop was for those that had little to no exposure to programmable hardware. For this situation I used two basic examples: two versions of a binary hello world.

The binary hello world -- blinking an LED -- is a good starting point to introduce programmable hardware, hardware descriptions languages,...

## Tool install for examples

August 2, 20132 comments

Most of my examples on fpgarelated use MyHDL for the hardware description and another Python package myhdl_tools rhea.build to control the FPGA vendor's software. This means everything is controlled and run from the Python environment.

Install the following to compile the posted examples:

MyHDL package : pip myhdl or myhdl github myhdl_tools : myhdl_tools bitbucket rhea...

## Shared-multiplier polyphase FIR filter

July 31, 20135 comments

Keywords: FPGA, interpolating decimating FIR filter, sample rate conversion, shared multiplexed pipelined multiplier

Discussion, working code (parametrized Verilog) and Matlab reference design for a FIR polyphase resampler with arbitrary interpolation and decimation ratio, mapped to one multiplier and RAM.

Introduction

A polyphase filter can be as straightforward as multirate DSP ever gets, if it doesn't turn into a semi-deterministic, three-legged little dance between input, output and...

## PC and SP for a small CPU

July 23, 2013

Ok, let's make a small stack-based CPU.

I will start where the rubber meets the road - the PC/stack subsystem that I like referring to as the 'legs'. As usual, I will present a design with a twist.

Not having a large design team, deadlines and million-dollar fab runs when designing CPUs creates a truly different environment. I can actually sit at the kitchen table and doodle around with CPU designs to my heart's content. I can try really ridiculous approaches, and work without a...

## What do Ohio, Python, and FPGAs have in common?

July 23, 2013

Anyone in the Columbus Ohio area in the United States this upcoming weekend (7/27 and 7/28) should stop by the @pyohio conference.  This is a *FREE* regional python conference.  I will be giving a talk at the end of the day Sunday, discussing MyHDL, FPGAs, and a hands-on workshop following the presentation.

The talk will focus on introducing programmable hardware to "imperative thinkers".  Anyone curious about FPGAs, Python, or familiar with FPGAs or embedded...

## How FPGAs work, and why you'll buy one

June 20, 201314 comments

Today, pretty much everyone has a CPU, a DSP and a GPU, buried somewhere in their PC, phone, car, etc. Most don't know or care that they bought any of these, but they did.

Will everyone, at some future point, also buy an FPGA? The market size of FPGAs today is about 1% of the annual global semiconductor sales (~$3B vs ~$300B). Will FPGA eventually...

## Learning VHDL - Basics

June 15, 20135 comments

Since FPGA are becoming more accessible to the hobbyist, learning how to use them can be really useful for certain applications, like DSP and video generation; moreover, engineers that are able to code in VHDL/Verilog are always requested on the job market.

In this tutorial I will cover the basics of Xilinx ISE and VHDL. I willl base my code on the Basys2 board from Digilent: it is really cheap (especially for students) and has a lot of features on board, as you can see from the picture...

## PicoBlaze - Program RAM Access for an Interactive Monitor

June 14, 20132 comments

I have a confession to make: I love PicoBlaze!  There are many reasons to love it.  It is a tiny CPU (96 Spartan3 slices or 26 Spartan6 slices plus a BRAM).  It is simple.  It is bug-free.  It's pretty fast.  It can reduce the size and the complexity of your design - instead of debugging a big state machine, just throw one (or more) of these in.  Add a serial output and you can debug your fpga from inside out!However, there are a few problems.  The...

## FPGA Bloggers Needed - New Reward System

April 11, 20112 comments

Are you an FPGA expert? If you are an have an interest in sharing your knowledge with the FPGA community, you might be interested in the new reward system for bloggers (see the blogs section here).

The rewards will be based on page impressions, meaning that the more traffic a blog post will get, the faster it will generate rewards for the author.

Basically, a given blog post will generate $25 to the author for every 250 unique pageviews, up to a maximum total reward of$500 per blog post...

## ESC Boston's Videos are Now Up

June 5, 2017

In my last blog, I told you about my experience at ESC Boston and the few videos that I was planning to produce and publish.  Here they are, please have a look and any feedback (positive or negative) is appreciated.

Short Highlight

This is a very short (one minute) montage of some of the footage that I shot at the show & conference.  In future shows, I absolutely need to insert clips here and there of engineers saying a few words about the conference (why they...

## Project introduction: Digital Filter Blocks in MyHDL and their integration in pyFDA

May 25, 20184 comments

Hi everyone! After a lot of hesitation and several failed attempts, I have finally entered the world of blogging. A little about myself : My name is Sriyash Caculo and I’m a third year undergrad student at BITS Pilani K.K. Birla Goa Campus  pursuing a major in Electronics and Instrumentation engineering. Being an electronics engineer, I developed an interest in Digital Signal Processing and its implementation on hardware.

This blog-post is the first of many to come for the...

## USB-FPGA : Introduction

January 12, 20111 comment

This blog is an introduction to a series of blogs I hope to write.  The blogs will cover the design and experiences I had on a project that spanned the last 6 years.  The project was the development of an USB FPGA board and the supporting gateware, firmware, and software.  The project has had different levels of activity over the years, ranging from none to some, but it has been an ongoing project, albeit, during sleepless nights.  Lately, I have ported the HDL (gateware)...

## Feedback Controllers - Making Hardware with Firmware. Part 7. Turbo-charged DSP Oscillators

January 5, 20187 comments
This article will look at some DSP Sine-wave oscillators and will show how an FPGA with limited floating-point performance due to latency, can be persuaded to produce much higher sample-rate sine-waves of high quality.

Comparisons will be made between implementations on Intel Cyclone V and Cyclone 10 GX FPGAs. An Intel numerically controlled oscillator

## Feedback Controllers - Making Hardware with Firmware. Part 2. Ideal Model Examples

August 24, 2017
Developing and Validating Simulation Models

This article will describe models for simulating the systems and controllers for the hardware emulation application described in Part 1 of the series.

## Part 11. Using -ve Latency DSP to Cancel Unwanted Delays in Sampled-Data Filters/Controllers

June 18, 201917 comments
This final article in the series will look at -ve latency DSP and how it can be used to cancel the unwanted delays in sampled-data systems due to such factors as Nyquist filtering, ADC acquisition, DSP/FPGA algorithm computation time, DAC reconstruction and circuit propagation delays.

Some applications demand zero-latency or zero unwanted latency signal processing. Negative latency DSP may sound like the stuff of science fiction or broken physics but the arrangement as...

## Tools of the Trade: reading PDFs (and keeping bookmarks)

July 7, 20155 comments

In this article I will take a look at the wonderful MuPDF viewer and present a small modification that saves bookmarks alongside the pdf files, making it infinitely more useful.

Some days I sit down to work and wonder how anything ever gets done. A simple example.  When I work on an FPGA design, I wind up with 3 or 4 screens full of documentation, generally in PDF format.  There are the Xilinx manuals, the various tool manuals, language reference manuals, you name it.  While...

## Yet another PWM

April 6, 20131 comment

## Helping New Bloggers to Break the Ice: A New Ipad Pro for the Author with the Best Article!

November 9, 2015

Breaking the ice can be tough.  Over the years, many individuals have asked to be given access to the blogging interface only to never post an article.  Maybe they underestimated the time it takes to write a decent article, or maybe they got cold feet. I don't blame or judge them at all - how many times in my life have I had the intention to do something but didn't follow through?  Once, maybe twice 😉 (don't worry if you don't...